Fault Injection Studies on Microprocessors: An Overview

Daniel Limbrick, an associate professor at North Carolina A&T, leads the ADEPT lab focusing on fault injection studies for microprocessors.
The lab investigates how radiation‑induced soft errors and physical faults can corrupt processor computations in critical domains such as space, military, and autonomous systems.
Understanding fault effects at the microprocessor level, rather than only at the circuit level, enables designers to assess reliability impacts on real applications like machine‑learning inference.
Key research questions include scalable fault modeling, identification of vulnerable nodes, efficient mitigation strategies, and evaluation of safety consequences for mission‑critical systems.
The lab combines physical design tools such as OpenLane with custom analysis pipelines to extract area, power, and timing data at each synthesis stage.
Fault injection is performed using RTL and gate‑level simulators, SAT‑based error propagation analysis, and probabilistic models that incorporate beam‑test generation rates.
To accelerate campaigns, the team converts designs to conjunctive normal form, XORs faulty and golden nets, and solves for satisfiability, achieving roughly fifteen‑fold speedups.
Mitigation techniques are applied during reliability‑aware synthesis and physical placement, including cell resizing, drive‑strength upgrades, and selective replacement with hardened standard cells.
The researchers also exploit unused routing gaps and timing slack to insert filters or larger cells without increasing area or critical‑path delay.
Experimental results on ISCAS‑85 benchmarks show that targeting a small fraction of vulnerable nodes can remove over eighty percent of soft‑error occurrences with less than one percent power overhead.
The ultimate goal is zero‑penalty reliability, meaning no measurable loss in performance, area, or power while achieving substantial error reduction.
Future work includes fabricating a PicoRV32 RISC‑V core in SkyWater 130 nm, where each core implements a different mitigation strategy for direct on‑chip comparison.
These chips will be integrated into tiny‑ML testbeds such as miniature self‑driving car demos to observe real‑time fault impacts on vision algorithms.
Overall, the ADEPT lab’s approach combines scalable fault modeling, fast injection pipelines, and design‑time hardening to enable reliable microprocessors for emerging safety‑critical applications.