Graduate student Nusra Akter Takia of the University of Florida presented.
Shrinking device dimensions and the shift toward heterogeneous, chiplet-based packaging have outpaced existing failure analysis methodologies, leaving a critical gap between die-level electrical test and package-level reliability characterization. This talk presents two complementary test vehicle platforms developed to close that gap. The first is a die-level test chip with deliberately engineered defects in metal interconnects, MOS transistors, and vias, built to calibrate nano-probing instrumentation and establish standardized failure signatures for nanoscale failure analysis. Building on this foundation, a second platform extends the same benchmarking approach to the packaging domain, embedding controlled defects across TSVs, micro-bumps, hybrid bonding interfaces, redistribution layers, and substrates to characterize reliability failure modes unique to advanced packaging technologies such as CoWoS and EMIB. Together, these platforms generate labeled, ground-truth defect datasets that enable multi-modal tool calibration and standardization and expose vulnerabilities to invasive probing introduced by fine-pitch interconnects, establishing a reference framework spanning the full IC-to-package integration stack.