SCALE SoCET Undergraduate Research Projects

This series includes three online presentations from the SoCET research projects. These inlcude:

• SCALE SoCET RISC-V Vector Extension

  The SCALE SoCET RISC-V Vector Extension is a design that aims to improve the performance and efficiency of vector operations on a RISC-V processor. The extension introduces a new vector register file with 128-bit width, which can be split into four lanes for memory access. This allows for efficient loading of data from memory, with each lane able to access 32 bits of data per cycle. The design also includes a bubble mechanism to handle cases where one or more lanes need to wait for memory access.
  The extension supports various vector operations such as add, multiply, and reduction instructions, as well as exception handling mechanisms. The design aims to minimize the number of cycles required to load data from memory, with an initial estimate of four cycles for a 128-bit load operation. The material also touches on the trade-offs between using a scalar cache versus a vector register file, highlighting the benefits of the latter in terms of improved performance and reduced area complexity. Overall, the SCALE SoCET RISC-V Vector Extension is designed to provide efficient and scalable support for vector operations on a RISC-V processor.

• SCALE SoCET Performance Modeling

  The teaching material "SCALE SoCET Performance Modeling" likely covers the process of modeling and simulating System-on-Chip (SoC) performance using various tools, with a focus on Gem5. The course may delve into the details of using Gem5 to simulate complex SoCs, including its strengths and weaknesses, such as its extensive documentation and support despite being "horrible" in some aspects. The material may also touch upon alternative simulators to Gem5, although it seems that Gem5 is the most popular choice for computer architecture simulation. The course might explore the computational intensity of Gem5 simulations, comparing them to full RTL (Register-Transfer Level) simulations, and discuss the potential benefits of using a simpler simulator like Gem5 for small chips. Additionally, the material may cover the process of customizing Gem5 for specific use cases, such as RISC-V modeling, and provide guidance on how to update and extend existing models for future extensions.

• SCALE SoCET Improving FPGA Area Through Look-up Table Optimizations

  The SCALE SoCET project aimed to improve FPGA area efficiency by optimizing look-up table (LUT) designs. The team focused on reducing LUT area by exploring different multiplexers (MUXs) that could be used in place of traditional 4-to-1 MUXs, which were found to be inefficient. Through experimentation and layout optimization, the team was able to squeeze out an additional 9 micrometer squared, representing a 4% reduction in area.
  The project also highlighted the importance of flip-flops as a major contributor to FPGA area consumption. The team proposed using latches instead of flip-flops, which are half the size, and potentially reducing area by up to 50%. Additionally, the project explored the use of structured data paths for routing, which could lead to denser designs if implemented correctly. Overall, the SCALE SoCET project demonstrated the potential for LUT optimizations to improve FPGA area efficiency, particularly in preparation for future process node migrations from 90nm to 12nm.