SCALE Comparison of Wide-Bandgap Semiconductor Devices Using Gate Charge Measurements

Graduate student Rick Cadena of Vanderbilt University presented at the Vanderbilt Seminar Series.

Wide‑bandgap semiconductor field‑effect transistors are central to modern high‑efficiency power converters, yet their switching behavior varies markedly with material system and device architecture. Comparing these devices requires a quantitative metric that captures the charge required to turn them on and off, making gate‑charge measurement a valuable diagnostic tool for researchers and designers alike.
The technique applies a constant gate current while the drain is biased and its current limited, producing a gate‑voltage‑versus‑gate‑charge trace that reveals three distinct regions. The initial slope reflects the gate‑to‑source capacitance (C gs), the plateau corresponds to the depletion of the Miller capacitance (C gd) as the device approaches its drain‑current limit, and the final rise incorporates both capacitances as the transistor fully conducts. By taking the inverse slope of the first segment and the combined slope of the plateau, one extracts C gs and C gd, while integration of the curve above a chosen gate voltage yields the energy dissipated during turn‑on and integration below gives the turn‑off loss. The method is demonstrated on cascode GaN‑FETs, silicon‑carbide MOSFETs, and research‑grade gallium‑oxide devices, illustrating how device‑specific phenomena such as drain‑induced barrier lowering affect the gate‑charge profile.