SCALE Assessing System-Level SET Response and Mitigation in SiGe Analog PLLs from Component-Level Response

Graduate student Delwyn Sam of Georgia Tech presented at the Vanderbilt Seminar Series.

Phase‑locked loops (PLLs) provide the fundamental timing and frequency‑synchronization mechanisms required for modern wireless and satellite communication systems operating across the radio‑frequency spectrum. Understanding how these circuits behave under radiation is critical for ensuring the reliability of high‑frequency analog and mixed‑signal electronics deployed in space and other harsh environments. This resource examines system‑level single‑event effects (SEEs) in silicon‑germanium (SiGe) analog PLLs and explores mitigation strategies derived from component‑level responses.
The presentation details the architecture of analog versus digital PLLs, emphasizing the absence of a charge‑pump in the analog topology and the resulting reliance on continuous‑time subcircuits such as the voltage‑controlled oscillator (VCO), frequency divider, and phase‑frequency detector (PFD). Experimental data are obtained from a 90‑nm Bi‑CMOS SiGe 9HP process chip fabricated at GlobalFoundries and irradiated with two‑photon‑absorption laser pulses (63–225 pJ, equivalent LET 1–14 MeV·cm⁻¹) at the U.S. Naval Research Laboratory. The study quantifies three SEE metrics—amplitude disturbance, phase displacement, and transient duration—by extracting waveform envelopes and phase shifts as functions of pulse energy, revealing that the VCO exhibits the largest amplitude perturbations while the PFD shows comparatively modest sensitivity. Circuit‑level simulations complement the measurements, providing insight into charge injection mechanisms and the propagation of single‑event transients through the PLL feedback loop.